Optimized memory addressing
AssigneeIntel Corporation
InventorsDavid E Freker, Aditya Sreenivas, Zohar Bogin, Anoop Mukker, Tuong Trieu
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Abstract
Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.
Claims14
A method of accessing memory comprising:
- accessing a first pair of adjacent data blocks of a first sequence of pairs of consecutive data blocks using a first channel of a dual channel memory device, the first channel having a data channel width, each data block having the same number of bits as the width of the data channel;
- and
- simultaneously accessing a second pair of adjacent data blocks of a second sequence of pairs of consecutive data blocks using a second channel of the memory device, the second channel having the same data channel width as the first channel and the data blocks of the second pair having the same number of bits as the data block in the first pair, the second pair being spaced apart from the first pair by a predetermined interval.
A machine-readable tangible storage medium having stored thereon data representing instructions which, when executed by a machine, cause the machine to perform operations comprising:
- accessing a first pair of adjacent data blocks of a first sequence of pairs of consecutive data blocks using a first channel of a dual channel memory device, the first channel having a data channel width, each data block having the same number of bits as the width of the data channel;
- and
- simultaneously accessing a second pair of adjacent data blocks of a second sequence of pairs of consecutive data blocks using a second channel of the memory device, the second channel having the same data channel width as the first channel and the data blocks of the second pair having the same number of bits as the data block in the first pair, the second pair being spaced apart from the first pair by a predetermined interval.
A method of mapping memory comprising:
- mapping a first pair of data blocks to a first channel of a dual channel memory;
- mapping a consecutive second pair of data blocks to a second channel of the dual channel memory;
- mapping a consecutive third pair of data blocks to the first channel of the dual channel memory;
- mapping a consecutive fourth pair of data blocks to the second channel of the dual channel memory;
- mapping a consecutive fifth pair of data blocks to the second channel of the dual channel memory;
- and
- mapping a consecutive sixth pair of data blocks to the first channel of the dual channel memory,
- wherein each channel has a data channel width corresponding to a number of bits and each data block has the same number of bits as the corresponding data channel width.
Dependencies are inferred from the claim text.