Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry

An imager comprising:

• a pixel array;
• sample and hold circuitry coupled to receive analog signals from pixels within the array;
• an amplification circuit for amplifying the analog signals;
• and
• a pipelined analog-to-digital converter connected to receive and convert the amplified analog signals to digital signals, said converter comprising:
• an amplifier,
• first and second pipeline stages adapted to be switchably connected to the amplifier in response to first and second clock signals,
• a discharge circuit adapted to cause a discharge operation to occur at an input of the amplifier in response to a reset pulse;
• and
• a clock generator, said clock generator generating first and second clock signals and a plurality of reset pulses, the first and second clock signals being generated such that they are non-overlapping, said clock generator applying the first and second clock signals and the reset pulses to the pipeline stages and the discharge circuit to change the connections between the pipeline stages, discharge circuit and the amplifier.