Method and system for decimating a pulse width modulated (PWM) signal

A method of decimating a Pulse Width Modulated (PWM) signal, the method comprising:

• computing at least one timestamp of the PWM signal, the PWM signal being at a first sample rate, the at least one timestamp being computed at a second sample rate, wherein the first sample rate is higher than the second sample rate;
• generating a plurality of pre-filter signals based on each of the at least one timestamp and a plurality of translation factors, a pre-filter signal being generated at the second sample rate having a frequency based on the second sample rate;
• filtering the plurality of pre-filter signals at the second sample rate using a plurality of Infinite Impulse Response (IIR) filters, each IIR filter corresponding to at least one translation factor of the plurality of translation factors, resulting in a plurality of intermediate decimated PCM signals;
• and
• wherein the computing step comprises:
• detecting at least one timestamp corresponding to at least one of each rising edge and each falling edge of the PWM signal;
• and
• applying an incremental phase correction to the at least one timestamp, wherein the incremental phase is based on a time period of the first sample rate and a time period of the second sample rate.

A method of decimating a Pulse Width Modulated (PWM) signal, the method comprising:

• computing at least one timestamp of the PWM signal, the PWM signal being at a first sample rate, the at least one timestamp being computed at a second sample rate, wherein the first sample rate is higher than the second sample rate;
• generating a plurality of pre-filter signals based on each of the at least one timestamp and a plurality of translation factors, a pre-filter signal being generated at the second sample rate having a frequency based on the second sample rate;
• filtering the plurality of pre-filter signals at the second sample rate using a plurality of Infinite Impulse Response (IIR) filters, each IIR filter corresponding to at least one translation factor of the plurality of translation factors, resulting in a plurality of intermediate decimated PCM signals;
• and
• wherein the generating step comprises:
• converting the at least one timestamp into a pre-filter signal based on at least one translation factor belonging to the plurality of translation factors;
• and
• changing a sign of the pre-filter signal corresponding to at least one falling edge of the PWM signal.

A method of decimating a Pulse Width Modulated (PWM) signal, the method comprising:

• computing at least one timestamp of the PWM signal, the PWM signal being at a first sample rate, the at least one timestamp being computed at a second sample rate, wherein the first sample rate is higher than the second sample rate;
• generating a plurality of pre-filter signals based on each of the at least one timestamp and a plurality of translation factors, a pre-filter signal being generated at the second sample rate having a frequency based on the second sample rate;
• filtering the plurality of pre-filter signals at the second sample rate using a plurality of Infinite Impulse Response (IIR) filters, each IIR filter corresponding to at least one translation factor of the plurality of translation factors, resulting in a plurality of intermediate decimated PCM signals;
• and
• wherein at least one IIR filter of the plurality of IIR filters is limited to unique poles.

A system for decimating a Pulse Width Modulated (PWM) signal, the system comprising:

• a timestamp detector for computing at least one timestamp of the PWM signal, the PWM signal being at a first sample rate, the at least one timestamp being computed at a second sample rate, wherein the first sample rate is higher than the second sample rate;
• a plurality of translators for generating a plurality of pre-filter signals based on each of the at least one timestamp and a plurality of translation factors, a pre-filter signal being generated at the second sample rate;
• a plurality of IIR filters for filtering the plurality of pre-filter signals at the second sample rate, each IIR filter corresponding to at least one translation factor of the plurality of translation factors, the filtering resulting in a plurality of intermediate decimated PCM signals;
• and
• a combiner for combining the plurality of intermediate decimated PCM signals to produce a PCM signal, the PCM signal being at the second sample rate.

A transceiver comprising:

• a timestamp detector for computing at least one timestamp of the PWM signal, the PWM signal being at a first sample rate, the at least one timestamp being computed at a second sample rate, wherein the first sample rate is higher than the second sample rate;
• a plurality of translators for generating a plurality of pre-filter signals based on each of the at least one timestamp and a plurality of translation factors, a pre-filter signal being generated at the second sample rate;
• a plurality of IIR filters for filtering the plurality of pre-filter signals at the second sample rate, each IIR filter corresponding to at least one translation factor of the plurality of translation factors, the filtering results in a plurality of intermediate decimated PCM signals;
• and
• a combiner for combining the plurality of intermediate decimated PCM signals to produce a PCM signal, the PCM signal being at the second sample rate.