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US 7,612,625 B2Granted
Bang-bang architecture
AssigneeIntel Corporation
InventorsMiaobin Gao, Yu-Li Hsueh, Chien-Chang Liu
Life of this patent
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Abstract
In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed.
Claims22
An apparatus comprising:
- a voltage controlled oscillator (VCO) including a first tank, wherein the first tank is to generate a first clock signal having a first frequency controlled by a bias current coupling ratio of a first bias current and a second bias current provided to the first tank;
- and
- a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio.
A method comprising:
- receiving a first signal in a control circuit responsive to an indication that a frequency of a voltage controlled oscillator (VCO) is different than a frequency of incoming data to a receiver including the VCO;
- generating a first control signal having a current value responsive to the first signal;
- and
- providing the first control signal to a first bias node of the VCO to adjust the VCO frequency in accordance with a change in a bias current coupling ratio between a first bias current and a second bias current, the first bias current including the first control signal.
1 more element
A system comprising:
- a clock and data recovery (CDR) circuit including:
- a detector to receive incoming data and a clock signal from a tank oscillator, the detector to generate first and second signals indicative of a frequency relationship between the incoming data and the clock signal;
- a controller coupled to receive the first and second signals from the detector and to generate a first adjustable current and a second adjustable current responsive thereto;
- and
- the tank oscillator to receive the first and second adjustable currents and to generate the clock signal having a frequency according to a ratio between a first bias current including the first adjustable current and a second bias current including the second adjustable current;
- and
- an optical-to-electrical converter coupled to the CDR circuit to provide the incoming data to the CDR circuit.
4 more elements
Dependencies are inferred from the claim text.