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US 7,612,621 B2Granted
System for providing open-loop quadrature clock generation
AssigneeInternational Business Machines Corporation
InventorsKyu-hyoun Kim, Paul W. Coteus, Daniel M. Dreps
Life of this patent
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Abstract
A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.
Claims12
A ring oscillator structure, the ring oscillator comprising:
- input inverters for receiving an input clock;
- forward direction loop inverters;
- backward direction loop inverters;
- one or more output nodes;
- and
- cross-coupled latches connected between any two opposite nodes,
- wherein the ring oscillator is preceded by a circuit to generate coarse quadrature clock phases from a differential input clock.
4 more elements
An open-loop clock generating circuit comprising:
- a coarse quadrature phase generating circuit for receiving a differential clock pair and generating a coarse four phase clock;
- one or more quadrature phase generating circuits in sequence for receiving the coarse four phase clock and for generating a four phase clock, the quadrature phase generating circuits each including forward direction loop inverters, backward direction loop inverters, output nodes, and cross-coupled latches connected between any two opposite nodes;
- an input level adjusting circuit preceding the coarse quadrature phase generating circuit for ensuring that the voltage levels on the differential clock have the same value of V-low and V-high relative to VDD.
A ring oscillator structure, the ring oscillator comprising:
- input inverters for receiving an input clock;
- forward direction loop inverters;
- backward direction loop inverters;
- one or more output nodes outputting a multiple phase clock;
- and
- cross-coupled latches connected between any two opposite nodes,
- wherein the ring oscillator is included in one or more of a memory controller, a hub device and a memory device, and data is transferred at a transfer rate that is equal to the greater of four and the number of output clock phases output at the one or more ring oscillator output nodes bits per clock cycle.
4 more elements
An open-loop clock generating circuit comprising:
- a coarse quadrature phase generating circuit for receiving a differential clock pair and generating a coarse four phase clock;
- one or more quadrature phase generating circuits in sequence for receiving the coarse four phase clock and for generating a four phase clock, the quadrature phase generating circuits each including forward direction loop inverters, backward direction loop inverters, output nodes, and cross-coupled latches connected between any two opposite nodes;
- and
- one or more twelve phase generating circuits for receiving the four phase clock and generating a twelve phase clock, the twelve phase generating circuits each including forward direction loop inverters, backward direction loop inverters, cross-coupled latches connected between any two opposite nodes and input inverters.
1 more element
An open-loop clock generating circuit comprising:
- a coarse quadrature phase generating circuit for receiving a differential clock pair and generating a coarse four phase clock;
- and
- one or more quadrature phase generating circuits in sequence for receiving the coarse four phase clock and for generating a four phase clock, the quadrature phase generating circuits each including forward direction loop inverters, backward direction loop inverters, output nodes, and cross-coupled latches connected between any two opposite nodes,
- wherein the open-loop clock generating circuit is included in one or more of a memory controller, a hub device and a memory device, and
- data is transferred to or from the memory device at a rate of four bits for every clock cycle.
2 more elements
Dependencies are inferred from the claim text.