System and method for conditioning differential clock signals and integrated circuit load board using same

A method of adjusting the relative phases of each of a plurality clock signals, comprising:

• comparing to each other a first set of clock signals that are assigned a predetermined phase difference to provide a first phase comparison signal indicative of the results of the comparison;
• comparing to each other a second set of clock signals that are assigned the predetermined phase difference to provide a second phase comparison signal indicative of the results of the comparison, at least one of the clock signals in the second set being different from the clock signals in the first set;
• comparing the first phase comparison signal to the second phase comparison signal;
• if the comparison of the first phase comparison signal to the second phase comparison signal has a first value, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the comparison of the clock signals in the first set or the comparison of the clock signals in the second set in a first direction;
• and
• if the comparison of the first phase comparison signal to the second phase comparison signal has a second value, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the comparison of the clock signals in the first set or the comparison of the clock signals in the second set in a second direction that is different from the first direction.

A method of conditioning a clock the method comprising:

• generating a plurality of pairs of complementary clock signals, each clock signal having a phase and a duty cycle;
• and
• alternating correcting the duty cycle of the clock signals in each of the plurality of pairs of complementary clock signals and setting the phases of the clock signals in each of the plurality of pairs of complementary clock signals until the duty cycle of the clock signals have been corrected and the phases of the clock signals have been set, the duty cycle of the clock signals being corrected and the phases of the clock signals being corrected by:
• selecting a first set of the clock signals that are assigned a predetermined phase difference;
• selecting a second set of the clock signals that are assigned the predetermined phase difference, at least one of the clock signals in the second set being different from the clock signals in the first set;
• generating a first phase comparison signal having a duty cycle corresponding to the phase relationship between the clock signals in the first set;
• generating a second phase comparison signal having a duty cycle corresponding to the phase relationship between the clock signals in the second set;
• generating first and second duty cycle voltages having respective magnitudes corresponding to the duty cycles of first and second clock signals in each of the pairs of complementary clock signals;
• generating first and second phase comparison voltages having respective magnitudes corresponding to the duty cycles of first and second phase comparison signals;
• comparing the magnitude of the first duty cycle voltage to the magnitude of the second duty cycle voltage;
• if the magnitude of the first duty cycle voltage is greater than the magnitude of the second duty cycle voltage, decreasing the duty cycle of the first clock signal and increasing the duty cycle of the second clock signal until the magnitude of the first duty cycle voltage is no longer greater than the magnitude of the second duty cycle voltage;
• if the magnitude of the second duty cycle voltage is greater than the magnitude of the first duty cycle voltage, increasing the duty cycle of the first clock signal and decreasing the duty cycle of the second clock signal until the magnitude of the second duty cycle voltage is no longer greater than the magnitude of the first duty cycle voltage;
• comparing the magnitude of the first phase comparison voltage to the magnitude of the second phase comparison voltage;
• if the magnitude of the first phase comparison voltage is greater than the magnitude of the second phase comparison voltage, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the phase relationship between the clock signals in the first set or the second set in a first direction until the magnitude of the first phase comparison voltage is no longer greater than the magnitude of the second phase comparison voltage;
• and
• if the magnitude of the second phase comparison voltage is greater than the magnitude of the first phase comparison voltage, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the phase relationship between the clock signals in the first set or the second set in a second direction that is opposite the first direction until the magnitude of the second phase comparison voltage is no longer greater than the magnitude of the first phase comparison voltage.

A system for conditioning clock signals in a plurality of complementary pairs of the clock signals, each clock signal having a phase and a duty cycle, the system comprising:

• a plurality of duty cycle correctors each of which receives the clock signals of a respective one of the pairs of clock signals, the duty cycles of the clock signals output from the duty cycle correctors being controlled by respective duty cycle control signals;
• a plurality of delay lines each of which receives the clock signals of a respective one of the pairs of clock signals, the phases of the clock signals output from the delay lines being controlled by respective phase control signals, each of the delay lines being coupled in series with a respective one of the duty cycle correctors;
• a first processing circuit having a plurality of input terminals, the first processing circuit being operable to generate at an output terminal a first phase comparison signal having a duty cycle corresponding to a phase relationship between clock signals applied to the input terminals of the first processing circuit;
• a second processing circuit having a plurality of input terminals, the second processing circuit being operable to generate at an output terminal a second phase comparison signal having a duty cycle corresponding to a phase relationship between clock signals applied to the input terminals of the second processing circuit;
• a comparison circuit having a plurality of input terminals, the comparison circuit being operable to compare the duty cycle of clock signals applied to the input terminals of the comparison circuit and to generate a comparison signal corresponding thereto;
• a controller coupled to receive the comparison signal from the comparison circuit, the controller being operable to apply to the duty cycle correctors the respective duty cycle control signals based on the comparison signal and to apply to the delay lines respective phase control signals based on the comparison signal;
• and
• a switching circuit coupled to receive the clock signals from the series combinations of a respective duty cycle correctors and delay lines, and to receive the first and second phase comparison signals from the first and second processing circuits, respectively, the switching circuit being operable in a duty cycle correcting mode to sequentially couple the clock signals of each of the pairs of clock signals to the input terminals of the comparison circuit, the switching circuit being operable in a phase adjustment mode to couple the first and second phase comparison signals of the first and second processing circuits, respectively, to the input terminals of the comparison circuit, the switching circuit further being operable in the phase adjustment mode to sequentially couple to the input terminals of the first processing circuit a first set of clock signals that are assigned a predetermined phase difference while coupling to the input terminals of the second processing circuit a second set of clock signals that are assigned the predetermined phase difference, at least one of the clock signals in the second set being different from the clock signals in the first set.

An integrated circuit load board, comprising:

• a substrate;
• a plurality of integrated circuit sockets mounted on the substrate;
• a clock source generating a plurality of complementary pairs of the clock signals, each clock signal having a phase and a duty cycle;
• a clock signal conditioning system coupled to receive the clock signals from the clock source, the clock signal conditioning system comprising:
• a plurality of duty cycle correctors each of which receives the clock signals of a respective one of the pairs of clock signals, the duty cycles of the clock signals output from the duty cycle correctors being controlled by respective duty cycle control signals;
• a plurality of delay lines each of which receives the clock signals of a respective one of the pairs of clock signals, the phases of the clock signals output from the delay lines being controlled by respective phase control signals, each of the delay lines being coupled in series with a respective one of the duty cycle correctors;
• a first processing circuit having a plurality of input terminals, the first processing circuit being operable to generate at an output terminal a first phase comparison signal having a duty cycle corresponding to a phase relationship between clock signals applied to the input terminals of the first processing circuit;
• a second processing circuit having a plurality of input terminals, the second processing circuit being operable to generate at an output terminal a second phase comparison signal having a duty cycle corresponding to a phase relationship between clock signals applied to the input terminals of the second processing circuit;
• a comparison circuit having a plurality of input terminals, the comparison circuit being operable to compare the duty cycle of clock signals applied to the input terminals of the comparison circuit and to generate a comparison signal corresponding thereto;
• a controller coupled to receive the comparison signal from the comparison circuit, the controller being operable to apply to the duty cycle correctors the respective duty cycle control signals based on the comparison signal and to apply to the delay lines respective phase control signals based on the comparison signal;
• and
• a switching circuit coupled to receive the clock signals from the series combinations of a respective duty cycle correctors and delay lines, and to receive the first and second phase comparison signals from the first and second processing circuits, respectively, the switching circuit being operable in a duty cycle correcting mode to sequentially couple the clock signals of each of the pairs of clock signals to the input terminals of the comparison circuit, the switching circuit being operable in a phase adjustment mode to couple the first and second phase comparison signals of the first and second processing circuits, respectively, to the input terminals of the comparison circuit, the switching circuit further being operable in the phase adjustment mode to sequentially couple to the input terminals of the first processing circuit a first set of clock signals that are assigned a predetermined phase difference while coupling to the input terminals of the second processing circuit a second set of clock signals that are assigned the predetermined phase difference, at least one of the clock signals in the second set being different from the clock signals in the first set;
• and
• an integrated test circuit mounted on the substrate and coupled to the integrated circuit sockets and to the clock signal conditioning system, the integrated test circuit being operable to apply test signals to the integrated circuit sockets and to receive response signals from the integrated circuit sockets, the integrated test circuit having an output port from which test results data derived from the response signals are output, the integrated test circuit being operable to alter the relative timing at which the test signals are applied to the integrated circuit sockets based on a plurality of clock signals received from the clock signal conditioning system.