US 7,612,598 B2 · Clock signal generation circuit and semiconductor device

Abstract

In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

Claims13

Dependent claims

A clock signal generation circuit comprising:

an edge detection circuit configured to detect an edge of an input signal;
a reference clock signal generation circuit configured to generate a reference clock signal;
a counter circuit configured to count the number of edges of the reference clock signal in accordance with a signal input from the edge detection circuit;
a duty ratio selection circuit configured to select a given duty ratio in accordance with a count value of the reference clock signal in the counter circuit;
and
a frequency division circuit configured to divide the reference clock signal and generate a clock signal having the duty ratio selected by the duty ratio selection circuit.

3 more elements

Dependencies are inferred from the claim text.

Clock signal generation circuit and semiconductor device

Life of this patent

Clock signal generation circuit and semiconductor device

Life of this patent

Abstract

Claims13