Internal clock generator

A memory device comprising:

• a clock buffer which buffers an external clock signal into a first internal clock signal having a first frequency;
• a frequency modulation unit coupled to the clock buffer which receives the first internal clock signal from the clock buffer and which uses the first internal clock signal to generate second and third internal clock signals having second frequencies that is lower than the first frequency;
• a transmission line coupled to the frequency modulation unit which transmits the second and third internal clock signals;
• and
• a clock generation unit coupled to the transmission line which receives the transmitted second and third internal clock signals from the frequency modulation unit via the transmission line and which outputs a fourth internal clock signal to at least one of:
• a row control unit for the memory device and a column control unit for the memory device in which the fourth internal clock signal has a frequency equal to that of the first frequency,
• wherein signal distortion is reduced by transmitting the second and third internal clock signals instead of transmitting the first internal clock signal, and
• wherein the fourth internal clock signal is applied to the row control unit and the column control unit and controls an operating time point of the row control unit and the column control unit.