Sequence independent non-overlapping digital signal generator with programmable delay

A circuit for generating non-overlapping clock signals, comprising:

• a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals;
• and
• a plurality of delay clock signal generators, operatively connected to said programmable delayed reference clock signals circuit to generate a plurality of non-overlapping clock signals;
• said plurality of delay clock signal generators controlling a delay in a rising edge of a non-overlapping clock signal independent of controlling a delay in a falling edge of the non-overlapping clock signal.

A method for generating non-overlapping clock signals, comprising:

• generating a plurality of delayed reference clock signals;
• generating, using the plurality of delayed reference clock signals, a plurality of non-overlapping clock signals;
• controlling a delay in a rising edge of a non-overlapping clock signal based upon a first delayed reference clock signal;
• and
• controlling a delay in a falling edge of a non-overlapping clock signal based upon a second delayed reference clock signal.