Programmable duty-cycle generator

A duty-cycle generator comprising:

• a duty-cycle adjustment circuit adapted to:
• receive an input clock signal having an input duty cycle;
• generate first and second versions of the input clock signal having different amounts of delay;
• and
• combine the first and second versions of the input clock signal to generate an output clock signal having an output duty cycle different from the input duty cycle;
• and
• a delay processor adapted to generate at least one control signal for controlling operations of the duty-cycle adjustment circuit based on a comparison of a characteristic of the output clock signal with a corresponding characteristic of a target output clock signal, wherein:
• the duty-cycle adjustment circuit comprises:
• a programmable delay line adapted to programmably delay the input clock signal to generate the first version of the input clock signal, wherein the amount of delay is based on one or more of the at least one control signal from the delay processor;
• and
• digital logic adapted to combine the first and second versions of the input clock signal to generate the output clock signal, wherein the digital logic comprises:
• logic adapted to generate a first combined version of the first and second versions of the input clock signal, wherein the first combined version corresponds to a logical OR operation of the first and second versions;
• logic adapted to generate a second combined version of the first and second versions of the input clock signal, wherein the second combined version corresponds to a logical AND operation of the first and second versions;
• and
• logic adapted to combine the first and second combined versions based on one or more of the at least one control signal from the delay processor to generate the output clock signal, wherein the one or more of the at least one control signal dictates whether the output duty cycle is greater than or less than the input duty cycle.

A duty-cycle generator comprising:

• a duty-cycle adjustment circuit adapted to:
• receive an input clock signal having an input duty cycle;
• generate first and second versions of the input clock signal having different amounts of delay;
• and
• combine the first and second versions of the input clock signal to generate an output clock signal having an output duty cycle different from the input duty cycle;
• a delay processor adapted to generate at least one control signal for controlling operations of the duty-cycle adjustment circuit based on a comparison of a characteristic of the output clock signal with a corresponding characteristic of a target output clock signal;
• and
• an averaging circuit adapted to provide an average value of the output clock signal over a predefined period of time, wherein the average value is used to generate the characteristic of the output clock signal, wherein the averaging circuit comprises:
• (i) at least one capacitor,
• (ii) a switch, and
• (iii) at least one resistor in parallel with the switch, wherein closure of the switch causes the output clock signal to bypass the resistor and to be provided directly to the capacitor.

A duty-cycle generator comprising:

• a duty-cycle adjustment circuit adapted to:
• receive an input clock signal having an input duty cycle;
• generate first and second versions of the input clock signal having different amounts of delay;
• and
• combine the first and second versions of the input clock signal to generate an output clock signal having an output duty cycle different from the input duty cycle;
• a delay processor adapted to generate at least one control signal for controlling operations of the duty-cycle adjustment circuit based on a comparison of a characteristic of the output clock signal with a corresponding characteristic of a target output clock signal;
• and
• a comparator adapted to compare the characteristic of the output clock signal with the characteristic of a target output clock signal, wherein the comparator comprises back-to-back dual metastability flip-flops adapted to provide additional settling time in generating a comparison result if the characteristic of the output clock signal is substantially identical to the characteristic of the target output clock signal.

A duty-cycle generator comprising:

• a duty-cycle adjustment circuit adapted to:
• receive an input clock signal having an input duty cycle;
• generate first and second versions of the input clock signal having different amounts of delay;
• and
• combine the first and second versions of the input clock signal to generate an output clock signal having an output duty cycle different from the input duty cycle;
• a delay processor adapted to generate at least one control signal for controlling operations of the duty-cycle adjustment circuit based on a comparison of a characteristic of the output clock signal with a corresponding characteristic of a target output clock signal;
• and
• a flip-flop adapted to store a result of the comparison, wherein the delay processor is adapted to provide the at least one control signal based on the stored result of a previous comparison instead of a result of a present comparison.