US 7,612,585 B2 · Pull-up circuit for an input buffer

Abstract

An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.

Claims16

Dependent claims

A pull-up circuit for an input buffer, comprising:

a pad;
a first PMOS transistor having a gate is directly electrically coupled to the pad and a source and a drain;
a second PMOS transistor having a source and a drain, wherein the first and second PMO transistors are coupled in series, and the drain of the second PMOS transistor is coupled to the pad;
a first node coupled to substrates of the first PMOS transistor and the second PMOS transistor;
a power supply coupled to the source of the first PMOS transistor;
and
a resistor coupled to a drain of a third PMOS transistor and coupled to the pad, where a source of the third PMOS transistor is coupled to power and a gate of the third PMOS transistor is coupled to the output of a PMOS-NMOS stack.

4 more elements

Dependencies are inferred from the claim text.

Pull-up circuit for an input buffer

Life of this patent

Pull-up circuit for an input buffer

Life of this patent

Abstract

Claims16