Semiconductor device, test system and method of testing on die termination circuit

A test system comprising:

• a termination impedance control circuit configured to generate a termination impedance control signal in response to a test mode command;
• an on die termination (ODT) circuit coupled to a plurality of pads and configured to generate a plurality of termination impedances in response to the termination impedance control signal;
• a semiconductor memory device that includes a boundary scan circuit configured to store the termination impedances to sequentially output the stored termination impedances;
• and
• a test device configured to generate the test mode command to be provided to the semiconductor memory device and configured to measure the termination impedances,
• wherein the termination impedances are sequentially outputted through one pin,
• wherein the boundary scan circuit includes boundary scan registers cascade-connected with each other, and
• wherein the boundary scan registers respectively store the termination impedances to sequentially output the termination impedances by a shifting operation.

A method of testing on die termination (ODT) circuit, the method comprising:

• generating a test mode command;
• generating a termination impedance control signal in response to the test mode command;
• generating a plurality of termination impedances in response to the termination impedance control signal;
• storing the termination impedances to output the stored termination impedances by using a boundary scan circuit;
• and
• measuring the termination impedances,
• wherein the termination impedances are sequentially outputted through one pin,
• wherein the boundary scan circuit includes boundary scan registers cascade-connected with each other, and
• wherein the boundary scan registers respectively store the termination impedances to sequentially output the termination impedances by a shifting operation.