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US 7,612,457 B2Granted
Semiconductor device including a stress buffer
AssigneeInfineon Technologies AG
InventorsJoachim Mahler, Alfred Haimerl, Angela Wieneke Kessler, Michael Bauer
Life of this patent
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Abstract
An integrated circuit includes a first surface configured for mounting to a carrier, an active area of the integrated circuit spaced from the first surface, a bond pad disposed over and in electrical communication with the active area, and a ceramic inorganic stress-buffering layer disposed between the active area and the bond pad.
Claims27
An integrated circuit configured to be mounted to a carrier, the integrated circuit comprising:
- a first surface configured for mounting to the carrier;
- an active area of the integrated circuit spaced from the first surface;
- a bond pad disposed over and in electrical communication with the active area;
- and
- a ceramic inorganic stress-buffering layer disposed between the active area and the bond pad, the ceramic inorganic stress-buffering layer comprising a hardness of greater than about 500 Kgforce/mm2 that is configured to minimize stress delivered to the active area when attaching a connector to the bond pad.
2 more elements
A semiconductor device comprising:
- a carrier;
- a chip including a first face and a second face opposite the first face, the first face coupled to the carrier and the second face including a metal contact layer disposed over an active area of the chip, a carbon stress-buffering layer disposed on the metal contact layer over the active area of the chip, and a bond pad disposed on the carbon stress-buffering layer.
A semiconductor device comprising:
- a carrier;
- a chip including a first face and a second face opposite the first face, the first face coupled to the carrier and the second face including an active area of the chip, and a bond pad disposed over the second face in electrical communication with the active area of the chip;
- and
- amorphous carbon means disposed between the active area of the chip and the bond pad for minimizing connector stress at the active area of the chip when bonding an electrical connector to the bond pad;
- wherein the amorphous carbon means comprises an electrical insulator.
2 more elements
A die package comprising:
- a carrier including contact pins;
- a chip including a first face and a second face opposite the first face, the first face coupled to the carrier and the second face including an active area of the chip, and a bond pad disposed over the second face in electrical communication with the active area of the chip;
- a connector extending between one of the contact pins and the bond pad;
- wherein the chip includes a ceramic inorganic material disposed between the active area of the chip and the bond pad, the ceramic inorganic material configured to minimize stress at the active area of the chip when connecting the connector to the bond pad.
1 more element
Dependencies are inferred from the claim text.