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US 7,612,435 B2Granted
Method of packaging integrated circuits
AssigneeNational Semiconductor Corporation
InventorsJaime A. Bayan, Anindya Poddar
Life of this patent
Estimating the term…
Abstract
A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead.
Claims17
An integrated circuit package, comprising:
- an integrated circuit die, the die having an active surface and a back surface substantially opposite the active surface, the active surface including a plurality of I/O pads;
- a lower leadframe including a plurality of lower contact leads, each lower contact lead having a first surface and a second surface substantially opposite the first surface, the first surface of each lower contact lead including at least one solder-wettable portion;
- an upper leadframe including a plurality of metal upper routing leads, each upper routing lead having a first surface and a second surface substantially opposite the first surface, the first surface of each upper routing lead including at least one inner solder-wettable portion and at least one outer solder-wettable portion, each inner solder-wettable portion being physically and electrically connected with an associated I/O pad by an associated solder joint, each outer solder-wettable portion being physically and electrically connected with an associated solder-wettable portion on the first surface of a lower contact lead by an associated solder joint such that each upper routing lead electrically couples an associated I/O pad with an associated lower contact lead, wherein at least most of the first surface of each upper routing lead is in direct contact with the molding material and wherein the first surface of each of the upper routing leads overlies at least most of the first surface of an associated lower contact lead.
An arrangement for packaging integrated circuit dice, comprising
- a first leadframe panel having a multiplicity of first device areas, each first device area having a plurality of first leads, the first leads of each first device area being arranged around an associated die attach area, each of the first leads having a first surface including a first solder pad surface;
- a multiplicity of integrated circuit dice having a plurality of I/O pads formed thereon, each die being positioned within an associated die attach area;
- a second leadframe panel having a multiplicity of second device areas, each second device area having a plurality of second leads, each of the second leads having a second surface including an inner second solder pad surface and an outer second solder pad surface, the second leadframe panel being positioned over the first leadframe panel such that the outer second solder pad surfaces are positioned over corresponding first solder pad surfaces of the first leadframe panel and such that the inner second solder pad surfaces are positioned over corresponding I/O pads, wherein the second surface of each of the second leads overlies at least most of the first surface of a corresponding first lead.
Dependencies are inferred from the claim text.