Overlapped stressed liners for improved contacts

A semiconductor structure including a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region, the semiconductor structure including a first gate conductor of the first semiconductor device extending over the first active semiconductor region and a second gate conductor of the second semiconductor device having an end joined to an end of the first gate conductor, the second gate conductor extending over the second active semiconductor region, the semiconductor structure further comprising:

• a first dielectric liner overlying the first semiconductor device;
• a second dielectric liner overlying the second semiconductor device, the second dielectric liner overlapping the first dielectric liner, the second dielectric liner including a first portion having a first thickness where the second dielectric liner overlies an apex of the second gate conductor, and including a second portion extending from rising peripheral edges of dielectric spacers disposed on walls of the second gate conductor, the second portion having a second thickness substantially greater than the first thickness, wherein the first dielectric liner has a tensile stress to apply a tensile stress to a channel region of the first semiconductor device and the second dielectric liner has a compressive stress to apply a compressive stress to a channel region of the second semiconductor device;
• a first conductive via contacting at least one of the first or second gate conductors, said conductive via extending through the first and second dielectric liners where the first and second dielectric liners are overlapped;
• and
• a second conductive via contacting at least one of a source region or a drain region of the second semiconductor device.