US 7,612,403 B2 · Low power non-volatile memory and gate stack

Abstract

Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Memory cells of the present invention also allow multiple bit storage. These characteristics allow memory device embodiments of the present invention to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

Claims59

Dependent claims

A non-volatile memory cell, comprising:

a first and second source/drain regions formed in a substrate coupled by a channel region;
an asymmetric band-gap tunnel insulator layer containing two or more sub-layers formed over the channel region and/or first and second source/drain regions, wherein the two or more sub-layers comprise layers of increasing conduction band offset;
a trapping layer formed over the tunnel insulator layer;
a charge blocking layer formed over the trapping layer;
and
a control gate formed over the charge blocking layer;
wherein the two or more sub-layers are formed so that the two or more sub-layers increase in conduction band offset from the trapping layer to the channel region.

4 more elements

A non-volatile memory device, comprising:

a non-volatile memory array containing a plurality of non-volatile memory cells formed into rows and columns, wherein one or more of the plurality of non-volatile memory cells comprises,
a first and second source/drain regions formed in a substrate coupled by a channel region,
an asymmetric band-gap tunnel insulator layer containing two or more sub-layers formed over the channel region and/or first and second source/drain regions,
wherein the two or more sub-layers comprise layers of increasing band offset,
a trapping layer formed over the tunnel insulator layer,
a charge blocking layer formed over the trapping layer, and
a control gate formed over the charge blocking layer,
wherein the two or more sub-layers are formed so that the two or more sub-layers increase in conduction band offset from the trapping layer to the channel region;
a memory interface;
and
a control circuit coupled to the memory interface and the non-volatile memory array.

8 more elements

A system, comprising:

a processor coupled to at least one non-volatile memory device, wherein the at least one non-volatile memory device comprises,
a non-volatile memory array containing a plurality of non-volatile memory cells formed into rows and columns, wherein one or more of the plurality of non-volatile memory cells comprises,
a first and second source/drain regions formed in a substrate coupled by a channel region,
an asymmetric band-gap tunnel insulator layer containing two or more sub-layers formed over the channel region and/or first and second source/drain regions,
wherein the two or more sub-layers comprise layers of increasing conduction band offset,
a trapping layer formed over the tunnel insulator layer,
a charge blocking layer formed over the trapping layer, and
a control gate formed over the charge blocking layer,
wherein the two or more sub-layers are formed so that the two or more sub-layers sequentially increase in conduction band offset from the trapping layer to the channel region;
a memory interface;
and
a control circuit coupled to the memory interface and the non-volatile memory array.

9 more elements

Dependencies are inferred from the claim text.

Low power non-volatile memory and gate stack

Life of this patent

Low power non-volatile memory and gate stack

Life of this patent

Abstract

Claims59