Nonvolatile memory semiconductor device and manufacturing method thereof
AssigneeRenesas Technology Corp.
InventorKazuyoshi Shiba
Life of this patent
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Abstract
To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned to form gate electrodes 7A, 7B, and then sidewall spacers 12 including a silicon oxide film are formed on sidewalls of the gate electrodes 7A, 7B. After that, a silicon nitride film 19 is deposited on a substrate 1 by a plasma enhanced CVD process so that the gate electrodes 7A, 7B are not directly contacted to the silicon nitride film 19.
Claims19
A semiconductor device comprising:
- a nonvolatile memory cell formed on a semiconductor substrate and having a first gate electrode including a first portion of a first conductive film, and a resistance element being formed on the semiconductor substrate and having a second portion of the first conductive film,
- wherein the nonvolatile memory cell has:
- first portions of a first insulating film formed over sidewalls of the first gate electrode,
- first semiconductor regions formed in the semiconductor substrate,
- first portions of a silicide layer formed over the first semiconductor regions,
- first portions of a second insulating film covering an area over the first gate electrode and the first portions of the first insulating film, and
- a third insulating film formed so as to cover the first portions of the silicide layer and the first portions of the second insulating film;
- and
- the resistance element has:
- second portions of the first insulating film formed over sidewalls of the second portion of the first conductive film,
- second portions of the second insulating film covering an area over the second portion of the first conductive film and over the second portions of the first insulating film, and having an opening on a part of the second portion of the first conductive film, and
- a second portion of the silicide layer formed on the part of the second portion of the first conductive film in the opening,
- wherein the third insulating film covers the second portions of the first insulating film, the second portions of the second insulating film, and the second portion of the silicide layer.
A semiconductor device comprising:
- a nonvolatile memory cell being formed on a first region of a semiconductor substrate, and a MISFET being formed on a second region of the semiconductor substrate,
- wherein the nonvolatile memory cell and the MISFET include:
- first conductor film portions formed at the first and second regions,
- first insulating film portions formed over sidewalls of the first conductor film portions,
- first semiconductor regions formed in the first and second regions,
- second insulating film portions being formed over the first conductor film portions at the first region and over the first insulating film portions formed over sidewalls of the first conductor film portions at the first region,
- silicide layer portions formed over the first semiconductor regions in the first and second regions and over the first conductor film portions at the second region,
- a third insulating film formed so as to cover the first insulating portions, the second insulating portions, and the silicide layer portions,
- a fourth insulating film formed over the third insulating film, and
- plugs formed in the third and fourth insulating films and electrically connected to the first semiconductor regions, and
- wherein the third insulating film is formed over the first conductor film portions at the first region without an intervening silicide layer portion.
A semiconductor device comprising a nonvolatile memory cell having a capacitance element formed over a first region of a semiconductor substrate and an element for writing data formed over a second region of the semiconductor substrate, the nonvolatile memory cell including:
- first insulating film portions formed over the first and second regions;
- a floating gate formed over the first insulating film portions of the first and second regions;
- first sidewall spacers formed over sidewalls of the floating gate;
- first semiconductor regions formed in the first region of the semiconductor substrate;
- a second semiconductor region formed in the second region of the semiconductor substrate;
- a second insulating film portion formed over the floating gate and the first sidewall spacers;
- silicide layer portions formed over the first semiconductor regions;
- a third insulating film formed over the second insulating film portion, the first sidewall spacers, and the silicide layer portions;
- a fourth insulating film formed over the third insulating film;
- and
- a plurality of plugs formed in the third and fourth insulating films such that each plug is electrically connected with a corresponding one of the first and second semiconductor regions,
- wherein the first semiconductor regions are part of a control gate of the nonvolatile memory cell,
- wherein the second semiconductor region is electrically connected to a data line of the non-volatile memory cell, and
- wherein the third insulating film is formed over the floating gate without any intervening silicide layer portion.
Dependencies are inferred from the claim text.