Optimized circuit design layout for high performance ball grid array packages

A method of laying out traces for connection of bond pads of a semiconductor chip to a ball grid array disposed on a substrate, which comprises the steps of:

• (a) providing a substrate having a surface with a plurality of rows and columns of ball pads and having a solder ball secured to each of said ball pads;
• and
• (b) providing a plurality of pairs of traces on said surface, each trace of each of said pairs of traces extending to a different one of said ball pads and extending to ball pads on a plurality of said rows and columns, each trace of each of said pair of traces being spaced from the other trace of said pair by up to a ball pitch, being maximized for identity in length and having up to one ball pitch difference in length and being maximized for parallelism and spacing;
• wherein said substrate has at least first, second and third rows and first, second, third and fourth columns of said ball pads in a matrix array, a first trace of a first pair of said traces extending to a ball pad in said first row of said second column closest to said chip and a second trace of said first pair of traces extending to a ball pad in said second row of said second column and between said first column and second column which is adjacent to said first column, a first trace of a second pair of said traces extending to a ball pad in said first row of said third column closest to said chip and a second trace of said second pair of traces extending to a ball pad in said second row of said third column and between said third column and said fourth column which is adjacent to said third column, and first and second traces of a third pair of said traces extending to ball pads in said third row of said second and third columns and disposed between said second and third columns.