Method for fabricating semiconductor wafer with enhanced alignment performance
AssigneeMacronix International Co., Ltd.
InventorChin-Cheng Yang
Life of this patent
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Abstract
A manufacturing method of a semiconductor wafer includes forming a plurality of alignment trenches in the wafer substrate. A dielectric layer is formed over the substrate filling the trenches. A planarization process is performed to remove the dielectric layer above the substrate. A photolithograph process is subsequently performed to selectively remove the dielectric layer formed in the trenches in the alignment area.
Claims15
A method for fabricating a semiconductor wafer having an alignment area, the method comprising:
- forming a dielectric layer over a surface of a substrate;
- forming a trench in the substrate of the alignment area;
- forming a liner layer to line the trench;
- forming a material layer covering the substrate and filling the trench;
- removing a portion of the material layer above the substrate;
- performing a photolithograph and etching process to remove a remaining portion of the material layer in the trench, wherein the photolithograph and etching process is only performed at the alignment area;
- and
- removing the dielectric layer subsequent to the removal of the remaining portion of the material layer in the trench.
A method for fabricating a semiconductor wafer, the method comprising:
- providing a substrate having an alignment area and a device area;
- forming a second dielectric layer on a surface of the substrate;
- forming a plurality of first trenches as alignment marks in the alignment area and a plurality of second trenches in the device area, wherein each alignment mark comprises a step height;
- forming a liner layer to line the first trenches and the second trenches;
- forming a first dielectric layer over the substrate filling the first and the second trenches;
- performing a planarization process to remove a portion of the first dielectric layer above the substrate;
- performing a photolithograph and etching process to remove the first dielectric layer remaining in the first trenches, wherein the photolithograph and etching process is only performed at the alignment area;
- and
- removing the second dielectric layer after the photolithograph and etching process.
A method for fabricating a semiconductor wafer, the method comprising:
- providing a substrate having an alignment area and a device area;
- forming a first dielectric layer over the substrate surface;
- forming a plurality of alignment marks in the alignment area and at least a first trench in the device area, wherein each alignment mark comprises at least a second trench;
- forming a liner layer to line the first trenches and the second trenches;
- forming a second dielectric layer over the substrate filling the first and the second trench;
- performing a planarization process to remove a portion of the second dielectric layer above the substrate;
- performing a photolithograph and etching process to remove the second dielectric layer in the second trench, wherein the photolithograph and etching process is only performed at the alignment area;
- and
- removing the first dielectric layer subsequent to the removal of the second dielectric layer in the second trench.
Dependencies are inferred from the claim text.