Method for manufacturing a memory cell arrangement

A method for manufacturing a memory cell arrangement, comprising:

• forming a charge storing memory cell layer stack over a substrate;
• forming first and second select structures over, respectively, first and second sidewalls of the charge storing memory cell layer stack, wherein the first and second select structures in each case comprise a select gate configured as a spacer and laterally disposed from the respective sidewall of the charge storing memory cell layer stack;
• removing a portion of the charge storing memory cell layer stack between the first and second select structures after formation of the first and second select structures, thereby forming first and second charge storing memory cell structures;
• forming an oxide layer over sidewalls of the first and second charge storing memory cell structures that are distant from the select structures, after removing the portion of the charge storing memory cell layer stack;
• and
• forming an electrically conductive layer over the oxide layer between the first and second charge storing memory cell structures.