Method of minimizing kerf width on a semiconductor substrate panel
AssigneeSanDisk Corporation
InventorsChih-Chin Liao, Ning Ye, Cheemen Yu, Jack Chang Chien, Hem Takiar
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Abstract
A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.
Claims27
A method of minimizing kerf width in a panel of substrate panel including a plurality of package outlines defining locations for formation of semiconductor packages, the method comprising:
- (a) forming a plating bar on the substrate panel between first and second adjacent package outlines, said forming step comprising forming the plating bar along its entire length closer to the first package outline than the second package outline;
- and
- (b) electrically coupling the plating bar to electrical terminals in the second package outline and not electrically coupling the plating bar to electrical terminals in the first package outline.
A method of minimizing kerf width in a panel of substrate panel including a plurality of package outlines defining locations for formation of semiconductor packages, the method comprising:
- (a) forming a plating bar on the substrate panel between first and second adjacent package outlines, said forming step comprising forming the plating bar closer to the first package outline than the second package outline;
- (b) electrically coupling the plating bar to electrical terminals in the second package outline and not electrically coupling the plating bar to electrical terminals in the first package outline, and each of said first and second package outlines including electrical terminals coming from at most two plating bars;
- and
- (c) cutting the electrical coupling between the electrical terminals in the second package outline and the plating bar, said step (c) of cutting having a tolerance by which the cut may vary from the intended cut line, the plating bar being formed sufficiently close to the first package in said step (a) to prevent electrical shorting together of two or more electrical terminals on the second package outline through the plating bar as a result of the tolerance of the cut.
A method of forming a semiconductor package including a substrate, the method comprising:
- (a) forming a plating bar on the substrate panel between first and second adjacent package outlines, said forming step comprising forming the plating bar closer to the first package outline than the second package outline;
- (b) electrically coupling the plating bar to electrical terminals in the second package outline and not electrically coupling the plating bar to electrical terminals in the first package outline;
- (c) electrically coupling electronic components to at least some of the electrical terminals in the second package outline;
- and
- (d) cutting the electrical coupling between the electrical terminals in the second package outline and the plating bar.
Dependencies are inferred from the claim text.