Method of improving post-develop photoresist profile on a deposited dielectric film

A method for depositing a material on a substrate, the method comprising:

• placing a substrate on a substrate holder in a chamber having a plasma source, wherein the plasma source comprises an RF source coupled to an upper electrode and the substrate holder comprises a bottom electrode coupled to a second RF source;
• introducing first processing gases into the chamber using a shower plate assembly coupled to the chamber, wherein the first processing gases include a trimethylsilane (3MS) precursor and Helium (He) gas;
• establishing an operating pressure in the chamber, the operating pressure being established at approximately 5 Torr,
• depositing a bottom layer portion of a Tunable Etch Resistant ARC (TERA) layer on the substrate, wherein the first processing gases are provided to the chamber, and the RF source is operated at a power level of approximately 800 watts, the second RF source is operated at a power level of approximately 30 watts, the shower plate assembly having a center region, an edge region, and a sub region configured to establish a first flow rate for the 3MS precursor between approximately 0 sccm and approximately 350 sccm and to establish another first flow rate for the He gas between approximately 0 sccm and approximately 600 sccm when the bottom layer portion is deposited;
• introducing second processing gasses into the chamber using the shower plate assembly, the second processing gases including the 3MS precursor, CO2 gas, and the He gas;
• depositing a top layer portion of the TERA layer on the substrate, wherein the second processing gases are provided to the chamber, and the RF source is operated at a power level of approximately 400 watts, the center region, the edge region, and the sub region being further configured to establish a second flow rate for the 3MS precursor between approximately 0 sccm and approximately 75 sccm to establish a flow rate for the CO2 gas between approximately 0 sccm and approximately 50 sccm and to establish a second flow rate for the He gas between approximately 0 sccm and approximately 600 sccm while depositing the top layer portion;
• performing at least one purging process, wherein the RF source is operated at approximately zero watts, an ESC voltage is approximately 0 volts, and the center region, the edge region, and the sub region are further configured to establish a third flow rate for the He gas between approximately 0 sccm and approximately 300 sccm;
• performing an evacuation process, wherein the RF source is operated at approximately zero watts, and the operating pressure is established below approximately 2 Torr;
• introducing third processing gases into the chamber using the shower head assembly, the third processing gases including CO2 gas, and He gas;
• establishing a post-processing pressure in the chamber, the post-processing pressure being established at approximately 2 Torr,
• establishing a post-processing plasma in the chamber, wherein the third processing gases are provided to the chamber the RF source is operated at a power level of approximately 30 watts, and the center region, the edge region, and the sub region are further configured to establish a fourth flow rate for the CO2 gas between approximately 0 sccm and approximately 40 sccm and to establish another fourth flow rate for the He gas between approximately 0 sccm and approximately 600 sccm during the post-processing plasma;
• modifying a top surface of the top layer portion of the deposited TERA layer by exposing the top layer portion of the deposited TERA layer to the post-processing plasma during the establishing step;
• performing a pin up process while the post-processing plasma is established, wherein the substrate is lifted off the substrate holder using one or more lift pins;
• and
• further modifying the top surface of the top layer portion of the deposited TERA layer by exposing the top surface of the top layer portion of the deposited TERA layer to the post-processing plasma during the pin up process step, wherein the modified top surface is created on the top surface of the top layer portion of the deposited TERA layer to prevent a photoresist problem during a subsequent lithographic operation.