Method and system for simulating state retention of an RTL design

A computer program product for simulating a circuit, comprising a medium storing computer programs for execution by one or more computer systems having at least a processing unit, a user interface and a memory, the computer program product comprising:

• code for receiving a netlist description of the circuit, wherein the netlist description is represented in a register-transfer-level (RTL) design environment;
• code for receiving power information specifications of the circuit;
• code for identifying one or more power domains of the circuit using the netlist description and the power information specifications;
• code for associating the one or more power domains and the power information specifications in the RTL design environment, wherein the one or more power domains are controlled by a set of power control signals through a power manager logic;
• and
• code for simulating state retention behavior in response to variations in power applied to a power domain, wherein the code for simulating state retention behavior includes:
• code for stopping a clock signal that controls sequential elements in the power domain in response to a clock gating signal being asserted;
• code for freezing values of the sequential elements in the power domain;
• and
• code for storing the values of the sequential elements.

A computer system for simulating a circuit, the computer system including a processor with memory and a computer-readable medium storing computer programs for execution by the computer system, the computer programs comprising:

• code for receiving a netlist description of the circuit, wherein the netlist description is represented in a register-transfer-level (RTL) design environment;
• code for receiving power information specifications of the circuit;
• code for identifying one or more power domains of the circuit using the netlist description and the power information specifications;
• code for associating the one or more power domains and the power information specifications in the RTL design environment, wherein the one or more power domains are controlled by a set of power control signals through a power manager logic;
• and
• code for simulating state retention behavior in response to variations in power applied to a power domain, wherein the code for simulating state retention behavior includes:
• code for stopping a clock signal that controls sequential elements in the power domain in response to a clock gating signal being asserted;
• code for freezing values of the sequential elements in the power domain;
• and
• code for storing the values of the sequential elements.