Chip design verification apparatus and data communication method for the same

A data communication method for a chip design verification apparatus for verifying a target unit including a hardware block, including a software block having at least one function block, a chip design verification program for verifying operations of the software block and the hardware block, a storage means of storing input and output data of the software block generated by executing the chip design verification program, and an interface means of performing an interfacing operation between the hardware block and the software block, the method comprising:

• a clock generation step of allowing the chip design verification program to obtain a multi clock setting value to be provided to the interface means, and generate multi clocks in response to a system clock of the chip design verification program and the multi clock setting value to be applied to the software block, and allowing the interface means to generate multi clocks in response to the system clock of the interface means and the multi clock setting value to be applied to the hardware block;
• a software side operation step of transmitting output data generated by the operation of the software block operating in response to the multi clocks of the chip design verification program to the interface means, determining whether the output data of the hardware block received via the interface means is valid by executing the chip design verification program, and applying only the valid output data of the hardware block to the software block;
• and
• a hardware side operation step of transmitting output data generated by the operation of the hardware block operating in response to the multi clocks of the interface means to the software block, determining whether the output data of the software block received is valid by executing the chip design verification program in the interface means, and applying only the valid output data of the software block to the hardware block, wherein the output data of the hardware block has an output value of the hardware block changed in response to the multi clocks applied from the interface means and a system clock count value of the interface means when the output value of the hardware block is changed.