Methods and apparatus for making placement sensitive logic modifications

A system for implementing a placement sensitive engineering change to meet design for test requirements the system comprising:

• a chip database for storing an already placed chip design;
• an engineering change database for storing all engineering change order for the already placed chip design;
• a tool database and a programmed processor comprising:
• means for placing a set of new flops in the already placed chip design to meet functional requirements of an engineering change;
• means for pruning the already placed chip design to create a set of valid flops and valid scan chains based on a set of pruning rules;
• means for generating a unified flop database containing physical location and connection information for the new flops and set of valid flops;
• means for generating a change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops meeting allocation and placement sensitive signal connection rules;
• and
• means for connecting the new flops to the selected valid flops allowing design for test requirements to be met.

A computer-readable medium storing a computer program which causes a computer system to perform a method for making a placement sensitive engineering change to meet design for test requirements, the computer-readable medium comprising:

• placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change;
• pruning the already placed chip design to create a set of valid flops and valid scan chains based on a set of pruning rules;
• generating a unified flop database containing physical location and connection information for the new flops and the set of valid flops;
• generating a change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops meeting allocation and placement sensitive signal connection rules;
• and
• connecting the new flops to the selected valid flops allowing design for test requirements to be met.