Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs

A system for converting between an asynchronous circuit design and a synchronous circuit design, comprising:

• a synchronous design file comprising multiple clock domains;
• a synthesis tool connected to receive the synchronous design file and generate a synchronous netlist of the synchronous design;
• and
• a converter connected to receive the synchronous netlist and to convert the synchronous netlist to an asynchronous design, the converter configured to determine a repeating period that corresponds to a least common multiple of all clock cycle times.

A system for converting between an asynchronous circuit design and a synchronous circuit design, comprising:

• means for identifying a synchronous design comprising multiple clock domains;
• means for generating a synchronous netlist of the synchronous design;
• and
• means for converting the synchronous netlist to an asynchronous design, the means for converting including means for determining a repeating period that corresponds to a least common multiple of all clock cycle times.

A program product comprising a computer-readable storage medium for converting between an asynchronous circuit design and a synchronous circuit design, the program product comprising a computer-readable storage medium operative by a computer and storing control instructions operative on the computer, which when executed cause the computer to perform:

• identifying a synchronous design comprising multiple clock domains;
• generating a synchronous netlist of the synchronous design;
• and
• converting the synchronous netlist to an asynchronous design, the converting including determining a repeating period that corresponds to a least common multiple of all clock cycle times.