Erasure generation in a forward-error-correcting communication system

An integrated circuit device comprising:

• first and second memories;
• a receiver to receive a first data packet from an external source;
• and
• a packet processing circuit to (1) store the first data packet within the first memory starting at a first address that is determined by the size of one or more previously received data packets, and (2) update an error descriptor value within the second memory, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies.

Computer-readable media having information embodied therein that includes a description of an integrated circuit device, the information including descriptions of:

• first and second memories;
• a receiver to receive a first data packet from an external source;
• and
• a packet processing circuit to (1) store the first data packet within the first memory starting at a first address that is determined by the size of one or more previously received data packets, and to (2) update an error descriptor value within the second memory, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies.

An integrated circuit device comprising:

• first storage means for storing packet data;
• second storage means for storing error information;
• means for receiving a first data packet from an external source;
• means for storing the first data packet within the first storage means starting at a first address that is determined by the size of one or more previously received data packets;
• and
• means for updating an error descriptor value within the second storage means, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies.