Method and apparatus for testing multi-core microprocessors

A computer program product comprising:

• a computer readable storage medium having stored thereon computer usable program code for testing a first set of communication bus interfaces and a first set of processor cores in a multiprocessor, the computer program product comprising:
• computer usable program code for initiating testing on the first set of processor cores on the multiprocessor in which the first set of communication bus interfaces is enabled to allow test results from the first set of processor cores to be communicated to a processor bus, and a second set of communication bus interfaces associated with a second set of processor cores not being tested are disabled such that the second set of processor cores can receive an input data from the processor bus but cannot send an output to the processor bus, wherein enabling the first set of communication bus interfaces and disabling the second set of communication bus interfaces are in accordance with a set of isolation test sequences;
• computer usable program code for identifying a set of functional processor cores in the set of processor cores based upon the test results;
• and
• computer usable program code for initiating a logic built-in self-test to test a communication bus interface in the first set of communication bus interfaces associated with a functional processor core in the set of functional processor cores, wherein the communication bus interface in the first set of communication bus interfaces is enabled and wherein the logic built-in self-test determines if the communication bus interface from the set of communication bus interfaces associated with the functional processor core in the set of functional processor cores is functional.

An apparatus for testing first set of communication bus interfaces and a first set of processor cores in a multiprocessor, the apparatus comprising:

• a computer comprising:
• a processor bus;
• a storage device connected to the processor bus, wherein the storage devices contains a computer usable program product;
• a processor unit, wherein the processor unit executes the computer usable program product to initiate testing on the first a set of processor cores on the multiprocessor in which the first set of communication bus interfaces is enabled to allow test results from the first set of processor cores to be communicated to the processor bus, and a second set of communication bus interfaces associated with a second set of processor cores not being tested are disabled such that the second set of processor cores can receive an input data from the processor bus but cannot send an output to the processor bus, wherein enabling the first set of communication bus interfaces and disabling the second set of communication bus interfaces are in accordance with a set of isolation test sequences;
• identify a set of functional processor cores in the set of processor cores based upon the test results;
• and initiate a logic built-in self-test to test a communication bus interface in the first set of communication bus interfaces associated with a functional processor core in the set of functional processor cores, wherein the communication bus interface in the first set of communication bus interfaces is enabled and wherein the logic built-in self-test determines if the communication bus interface from the set of communications bus interfaces associated with the functional processor core in the set of functional processor cores is functional.