US 7,610,532 B2 · Serializer/de-serializer bus controller interface

Abstract

An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core logic. In addition to the dedicated interface, the ASIC includes a controller responsive to a set of signals and a plurality of receivers distributed about the SBus. Each of the receivers is responsive to a set of commands that can be reused to test logic and support functions across each revision of the ASIC as well as to test separate ASICs with similar arrangements of support functions without requiring the generation of a distinct scan vector to test the ASIC. Additional interfaces, such as an I.E.E.E. 1149.1 interface, further extend SBus capabilities to external test equipment.

Claims20

Dependent claims

An application-specific integrated circuit (ASIC), comprising:

a Serializer/De-serializer bus (SBus) independent of core logic and support blocks on the ASIC, the SBus comprising:
a controller configured with a SBus interface, a core logic interface a test access port interface, and a contention state machine configured to identify which of the core logic interface or the test access port interface will be granted controller resources, the core logic interface responsive to a set of signals and providing SBus capabilities to logical functions implemented in core logic of the ASIC, the controller and the core logic interface being asynchronous to each other;
and
a plurality of receivers distributed about the SBus.

1 more element

Dependencies are inferred from the claim text.

Serializer/de-serializer bus controller interface

Life of this patent

Serializer/de-serializer bus controller interface

Life of this patent

Abstract

Claims20