Test output compaction with improved blocking of unknown values
AssigneeNEC Laboratories America, Inc.
InventorsSeongmoon Wang, Kedarnath J Balakrishnan, Srimat T Chakradhar
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Abstract
Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.
Claims15
A method of configuring a test output compaction arrangement, the arrangement receiving test response data from a circuit after a test pattern is applied to the circuit, the arrangement comprising blocking logic interposed between the circuit and a temporal compactor, the blocking logic responsive to control signals from a control signal generator so as to selectively block test response data from propagating to the temporal compactor, the method comprising:
- identifying unknown values and fault effects in the test response data which would propagate to the temporal compactor when a test pattern in a set of test patterns is applied to the circuit;
- assigning specified bits in a control pattern associated with the test pattern to block the unknown values from entering the temporal compactor and to propagate selected fault effects to the temporal compactor, the fault effects selected so as to balance the number of specified bits across the set of test patterns, the control patterns with the assigned specified bits used to compute the control signals to be generated by the control signal generator for the blocking logic.
A method of configuring a test output compaction arrangement, the arrangement receiving test response data from a circuit after a test pattern is applied to the circuit, the arrangement comprising blocking logic interposed between the circuit and a temporal compactor, the blocking logic responsive to control signals from a control signal generator so as to selectively block test response data from propagating to the temporal compactor, the method comprising:
- determining whether a first control pattern used for seed computation for first control signals to block unknown values appearing in test response data, when a first test pattern is applied to the circuit, is compatible with a second control pattern used for seed computation for second control signals to block unknown values appearing in test response data, when a second test pattern is applied to the circuit, and
- if the first control pattern and the second control pattern are compatible, reusing a seed at the control signal generator to generate both the first and second control signals for the blocking logic.
Dependencies are inferred from the claim text.