US 7,610,526 B2Granted

On-chip circuitry for bus validation

AssigneeHewlett-Packard Development Company, L.P.

InventorsDerek A. Sherlock, Jayen J. Desai, Chih-Jen Chen

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Abstract

Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise a first logic configured to receive a test sequence of electrical signals from the bus, a second logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals, and a compare logic operably connected to the first logic and the second logic. The compare logic may be configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the test sequence and the check sequence.

Claims39

Dependent claims

A system, comprising:

a first circuit operably connected to a bus to be electrically validated, the first circuit comprising:
a first logic configured to selectively produce a test sequence of electrical signals that may be driven onto the bus;
a second logic configured to produce one or more bus protocol signals that may be driven onto the bus;
a bus interface logic operably connected to the first logic and the second logic, the bus interface logic being configured to drive the test sequence and the bus protocol signals onto the bus;
and
a test logic operably connected to one or more of the first logic, the second logic, and the bus interface logic, the test logic being configured to control the first circuit to select which of, the bus protocol signals, and the test sequence are driven onto the bus;
and
a second circuit operably connected to the bus, the second circuit comprising:
a third logic configured to receive from the bus a received sequence of electrical sequences produced by the bus interface logic driving the test sequence onto the bus;
a fourth logic configured to produce a check sequence of electrical signals related to the test sequence;
and
a bus verification logic operably connected to the third logic and the fourth logic, the bus verification logic being configured to determine whether the bus is correctly transmitting digital data based, at least in part, on comparing the received sequence and the check sequence, and to produce a miscompare data configured to record information concerning parameters associated with determining that the bus is not correctly transmitting digital data, where the miscompare data comprises a bus line on which a miscompare occurred, where the miscompare data comprises a seed value employed by the fourth logic.

9 more elements

A system, comprising:

a first circuit operably connected to a bus to be electrically tested, the first circuit comprising:
a first logic configured to selectively produce a test sequence of electrical signals that may be driven onto the bus, the test sequence being selected from, a pseudorandom sequence, a walking ones sequence, a walking zeroes sequence, an alternating all ones sequence, an alternating all zeroes sequence, an alternating all ones sequence with a user selectable output always high, an alternating all ones sequence with a user selectable output always low, an alternating all zeroes sequence with a user selectable output always low, an alternating all zeroes sequence with a user selectable output always high, an alternating AA sequence, and an alternating 55 sequence, the first logic being configured to produce the test sequence in real time, synchronous with one or more clock circuits providing a timing signal in the first integrated circuit,
the first circuit being configured to receive a control signal operable to control a type of test sequence to produce, a test sequence length, an initial test sequence recognition sequence, when test sequence generating will begin, and when test sequence generating will end;
a second logic configured to produce bus protocol signals that may be driven onto the bus;
a bus interface logic operably connected to the first logic and the second logic, the bus interface logic being configured to selectively drive the test sequence and the bus protocol signals onto the bus;
and
a test logic operably connected to one or more of the first logic, the second logic, and the bus interface logic, the test logic being configured to control the first circuit to select which of, the bus protocol signals, and the test sequence are driven onto the bus;
and
a second circuit operably connected to the bus, the second circuit comprising:
a third logic configured to receive from the bus a received sequence of electrical signals produced by the bus interface logic driving the test sequence onto the bus;
a fourth logic configured to produce a check sequence of electrical signals related to the test sequence;
and
a bus verification logic operably connected to the third logic and the fourth logic, the bus verification logic being configured to determine whether the bus is operating correctly based, at least in part, on comparing the received sequence of electrical signals and the check sequence, the bus verification logic being configured to selectively produce an external trigger upon determining that the bus is not operating correctly, the bus verification logic being configured to selectively produce a miscompare data configured to record information concerning parameters associated with determining that the bus is not operating correctly where the miscompare data comprises a bus line on which a miscompare occurred, where the miscompare data comprises a seed value employed by the fourth logic;
the second circuit being configured to receive a control signal operable to control one or more of, a type of check sequence to produce, a check sequence length, an initial test sequence recognition sequence, a bus line for which testing is to be performed, an error mask to be employed, a type of miscompare data to acquire, whether a signal will be provided to an external device upon a miscompare, whether to acquire a pre-miscompare data, and whether to acquire a post-miscompare data.

11 more elements

An electrical circuit comprising:

a bus;
a first circuit portion connected to the bus, the first circuit portion comprising:
a first sub-circuit configured to produce a first set of electrical signals;
a second sub-circuit configured to produce one or more bus protocol signals;
an interface sub-circuit configured to drive the first set of electrical signals and the bus protocol signals onto the bus;
and
a third sub-circuit operably connected to one or more of, the first sub-circuit, the second sub-circuit, and the interface sub-circuit, the third sub-circuit being configured to control the first circuit portion to selectively disable driving the bus protocol signals onto the bus and to selectively enable driving the first set of electrical signals onto the bus;
and
a second circuit portion connected to the bus, the second circuit portion comprising:
a fourth sub-circuit configured to receive one or more electrical signals produced by driving the first set of electrical signals onto the bus;
a fifth sub-circuit configured to produce a second set of electrical signals identical to the first set of electrical signals;
and
a sixth sub-circuit operably connected to the fourth sub-circuit and the fifth sub-circuit, the sixth sub-circuit being configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the one or more received electrical signals and the second set of electrical signals, where the sixth sub-circuit is to record miscompare data comprising parameters associated with determining in real-time that the bus is not correctly transmitting digital data, the parameters store information indicating a bus line on which a miscompare occurred the miscompare data further comprising a seed value used for determining a sequence of the received one or more electrical signals.

10 more elements

A system, comprising:

a first logic configured to selectively produce a test sequence of electrical signals that may be driven onto a bus;
a second logic configured to produce one or more bus protocol signals that may be driven onto the bus;
a bus interface logic operably connected to the first logic and the second logic, the bus interface logic being configured to drive the test sequence of electrical signals and the bus protocol signals onto the bus;
a test logic operably connected to one or more of the first logic, the second logic, and the bus interface logic, the test logic being configured to selectively control which of the bus protocol signals and the test sequence of electrical signals are driven onto the bus;
a third logic configured to receive from the bus a received sequence of electrical sequences produced by driving the test sequence of electrical signals onto the bus;
a fourth logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals;
and
a bus verification logic operably connected to the third logic and the fourth logic, the bus verification logic being configured to determine whether the bus is correctly transmitting digital data based, at least in part, on comparing the received sequence and the check sequence, where the bus verification logic is to record miscompare data comprising parameters associated with determining that the bus is not correctly transmitting digital data, the parameters store information indicating a bus line on which a miscompare occurred the miscompare data further comprising a seed value employed by the fourth logic.

5 more elements

Dependencies are inferred from the claim text.