Defective memory block identification in a memory device
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location.
Claims19
A method for indicating a defective memory block in a memory array,
- the method comprising:
- checking the memory array for a defective memory block;
- and
- storing a defect indication of any defective memory blocks in a defect-free memory block.
A method for indicating a defective memory block in a memory array organized into a plurality of memory blocks, each block having a block indicator, the method comprising:
- performing a memory check for defective memory blocks;
- erasing the memory array;
- and
- storing, in a defect-free memory block, a listing of the block indicators of any defective memory blocks found by the memory check.
A method for indicating a defective memory block a memory array, the method comprising:
- checking the memory array for defective memory blocks;
- and
- storing, in each memory block, an indication of programmability regarding that memory block.
A memory device comprising:
- a memory array comprising a plurality of memory blocks;
- and
- control circuitry, coupled to the memory array, that is adapted to read at least one defect indication location in a first memory block of the plurality of memory blocks
- wherein each defect indication location contains a reference to a defective memory block of the plurality of memory blocks.
A memory device comprising:
- a memory array organized into a plurality of memory blocks;
- and
- control circuitry, coupled to the memory array, that is adapted to read at least one defect indication location in a first memory block of the plurality of memory blocks wherein each defect indication location contains a predetermined pattern indicating the programmability of the first memory block, the defect indication location comprising a plurality of data bytes.
An memory system comprising:
- a processor for generating memory signals;
- and
- a memory device coupled to the processor, the device comprising:
- a memory array organized into a plurality of memory blocks;
- and
- control circuitry, coupled to the memory array and the processor, that is adapted to read in response to the memory signals at least one defect indication location in a first memory block of the plurality of memory blocks wherein each defect indication location contains a reference to a defective memory block of the plurality of memory blocks.
Dependencies are inferred from the claim text.