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US 7,610,524 B2Granted
Memory with test mode output
AssigneeMicron Technology, Inc.
InventorJeffery W. Janzen
Life of this patent
Estimating the term…
Abstract
Methods of operating an apparatus allow a memory to generate a test mode signal to trigger a test, in response to the memory detecting a predetermined command from a system bus.
Claims39
A method comprising:
- receiving, at a memory device, information identifying a command for the memory device to monitor;
- loading the information into a register of the memory device during an initialization of the memory;
- setting an indicator at a storage location in the memory device, the indicator to enable or disable issuing a test mode signal in response to the memory device detecting the command from a system bus such that the test mode signal provides output from the memory device to an external device to trigger a test of the memory device using the external device.
A method comprising:
- monitoring a system bus in a memory device;
- decoding a command acquired from monitoring the system bus;
- comparing the command to a stored command in one or more registers of the memory device, the stored command at least in part indicative of a test mode;
- determining to issue a test mode signal;
- and
- generating the test mode signal in the memory device such that the test mode signal provides output from the memory device to an external device triggering a test of the memory device using the external device, the test mode signal generated in response to detecting the stored command as the command on the system bus and to determining to issue the test mode signal.
3 more elements
A method comprising:
- arranging a set of bits to send to a memory device to load into a register of the memory device such that the arranged set of bits includes data to issue a test mode signal that provides output from the memory device to an external device triggering a test of the memory device, using the external device, in response to the memory device detecting a predetermined command from a system bus;
- and
- outputting the set of bits directed to the memory device during an initialization of the memory device.
A computer-readable medium having computer-executable instructions for performing operations comprising:
- arranging a set of bits to send to a memory device to load into a register of the memory device such that the arranged set of bits includes data to issue a test mode signal that provides output from the memory device to an external device triggering a test of the memory device, using the external device, in response to the memory device detecting a predetermined command from a system bus;
- and
- outputting the set of bits directed to the memory device during an initialization of the memory device.
A computer-readable medium having computer-executable instructions stored thereon for performing operations comprising:
- controlling a memory device to issue a test mode signal from the memory device to an external device to trigger a test of the memory device using the external device, the memory device configured to issue the test mode signal in response to the memory device detecting a predetermined command from a system bus, wherein controlling the memory device includes using a data structure having a field containing data representing information operable with instructions to issue the test mode signal from the memory device to trigger the test of the memory device in response to the memory device detecting the predetermined command from the system bus.
Dependencies are inferred from the claim text.