Compliance of master-slave modes for low-level debug of serial links
AssigneeIntel Corporation
InventorsTimothy Frodsham, Zale Schoenborn, Sanjay Dabral, Muraleedhara H. Navada
Life of this patent
Estimating the term…
Abstract
A condition is detected to cause a component having physical layer circuitry with a transmitter and a receiver to enter a testing state. The transmitter transmits a pre-selected data pattern while comparing data received by the receiver to the pre-selected data pattern during a first phase of the testing state. The transmitter transmits data received by the receiver without comparing the data received by the receiver to the pre-selected data pattern during a second phase of the testing state.
Claims20
A method comprising:
- detecting a condition to cause a component having physical layer circuitry with a transmitter and a receiver to enter a testing state;
- causing the transmitter to transmit a pre-selected data pattern while comparing data received by the receiver to the pre-selected data pattern during a first phase of the testing state;
- and
- causing the transmitter to transmit data received by the receiver without comparing the data received by the receiver to the pre-selected data pattern during a second phase of the testing state.
An apparatus comprising:
- means for detecting a condition to cause a component having physical layer circuitry with a transmitter and a receiver to enter a testing state;
- means for causing the transmitter to transmit a pre-selected data pattern while comparing data received by the receiver to the pre-selected data pattern during a first phase of the testing state;
- and
- means for causing the transmitter to transmit data received by the receiver without comparing the data received by the receiver to the pre-selected data pattern during a second phase of the testing state.
A physical layer interface comprising:
- a transmission port to transmit data;
- a receiving port to receive data;
- comparison circuitry;
- and
- control circuitry coupled with the transmission port, with the receiving port, and with the comparison circuitry, the control circuitry to selectively enter a testing state having at least two phases, wherein during the first phase the control circuitry causes the transmission port to transmit a pre-selected data pattern and also to cause the comparison circuitry to compare data received by the receiving port to the pre-selected pattern, and further wherein during the second phase the control circuitry causes the transmission port to transmit data received by the receiving port.
A system comprising:
- a transmission port to transmit data;
- a receiving port to receive data;
- a dynamic random access memory;
- comparison circuitry;
- and
- control circuitry coupled with the transmission port, with the receiving port, with the comparison circuitry, and with the dynamic random access memory, the control circuitry to selectively enter a testing state having at least two phases, wherein during the first phase the control circuitry causes the transmission port to transmit a pre-selected data pattern and also to cause the comparison circuitry to compare data received by the receiving port to the pre-selected pattern, and further wherein during the second phase the control circuitry causes the transmission port to transmit data received by the receiving port.
Dependencies are inferred from the claim text.