Microprocessor with trace functionality
AssigneeInnovasic, Inc.
InventorAndrew David Alsup
Life of this patent
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Abstract
A trace function method for microprocessors is provided. The method is operable with a microprocessor comprising an execution unit operable in one or a plurality of contexts. The method comprises: providing a memory coupled to the execution unit, utilizing the memory to store trace data during a trace operation; and providing hardware utilizable during a trace operation to assist in the trace operation.
Claims50
A method for providing trace functionality for a microprocessor comprising an execution unit, said method comprising:
- providing a memory coupled to said execution unit,
- utilizing said memory to store trace data during a trace operation;
- providing hardware integrated with said microprocessor and utilizable during a trace operation to assist in said trace operation
- providing a trace control coupled to said execution unit and to said memory;
- providing a breakpoint control coupled to said execution unit, said trace control and said memory;
- providing a plurality of sets of programmable registers coupleable to said breakpoint control, and each set comprising a base address register, a data register, a data mask register and a control register;
- providing in said trace control a programmable trace control register and a programmable base write address register, said trace control register being programmable to determine one of a plurality of trace functions;
- and
- integrating said trace control, said breakpoint control and said plurality of sets of programmable registers with said execution unit.
A method for providing trace functionality for a microprocessor comprising an execution unit, said method comprising:
- providing a buffer memory coupled to said execution unit, said buffer memory utilized to store trace data during operation of said execution unit;
- providing a trace control coupled to said execution unit and to said buffer memory;
- providing a breakpoint control coupled to said execution unit, said trace control and said buffer memory;
- providing a plurality of sets of programmable registers coupleable to said breakpoint control, and each set comprising a base address register, a data register, a data mask register and a control register;
- providing in said trace control a programmable trace control register and a programmable base write address register, said trace control register being programmable to determine one of a plurality of trace functions.
A microprocessor, comprising:
- an execution unit operable in a plurality of contexts:
- a memory coupled to said execution unit, said memory utilized to store trace data during operation of said execution unit;
- a trace control coupled to said execution unit and to said memory;
- a breakpoint control coupled to said execution unit, said trace control and said memory;
- said breakpoint control comprising:
- a plurality of sets of programmable registers, each set of programmable registers being provided for a corresponding one context of said plurality of contexts and each set comprising a base address register, a data register, a data mask register and a control register;
- said trace control comprising a programmable trace control register and a programmable base write address register, said trace control register being programmable to determine one of a plurality of trace functions.
Dependencies are inferred from the claim text.