Semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a first power supply region supplied with a first power supply voltage, and having a first clock distribution network;
• a second power supply region supplied with a second power supply voltage, and having a second clock distribution network;
• a phase synchronizer which outputs an output signal obtained by making a phase of a reference clock signal for controlling data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network;
• and
• a first delay circuit driven by the second power supply voltage, the first delay circuit delaying the output signal by a first delay time and providing the delayed signal to a second point of the first clock distribution network;
• and
• a second delay circuit driven by the first power supply voltage, the second delay circuit delaying the output signal by a second delay time and providing the delayed signal to a first point of the second clock distribution network,
• wherein the semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage.

A semiconductor integrated circuit comprising:

• a first power supply region supplied with a first power supply voltage, and having a first clock distribution network;
• a second power supply region supplied with a second power supply voltage, and having a second clock distribution network;
• a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network;
• and
• a second phase synchronizer which provides a second output signal obtained by making the phase of the clock signal at a third point of the first clock distribution network coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network,
• wherein the semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage.