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US 7,610,497 B2Granted
Power management system with a bridge logic having analyzers for monitoring data quantity to modify operating clock and voltage of the processor and main memory
AssigneeVIA Technologies, Inc.
InventorsRuei-Ling Lin, Jiin Lai, Hung-Yi Kuo
Life of this patent
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Abstract
A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the state machine.
Claims19
A bridge logic for managing power consumption of a processor and a main memory, wherein the processor accesses the main memory through the bridge logic, the bridge logic comprising:
- a first buffer space for temporarily storing data from the processor;
- a second buffer space for temporarily storing data from the main memory;
- a first analyzer for monitoring data quantity of the first buffer space in a first period of time to determine if the data quantity of the first buffer space exceeds a first threshold value;
- a second analyzer for monitoring data quantity of the second buffer space in a second period of time to determine if the data quantity of the second buffer space exceeds a second threshold value;
- and
- a power management unit, coupled to the first analyzer and the second analyzer, for modifying an operating clock and an operating voltage of the processor and an operating clock and an operating voltage of the main memory based on information from the first analyzer and the second analyzer.
3 more elements
A computer system for power management, comprising:
- a processor;
- a main memory;
- a bridge logic coupled between the processor and the main memory, wherein the processor accesses the main memory through the bridge logic;
- and
- a southbridge logic coupled to the bridge logic,
- wherein the bridge logic comprises:
- a first buffer space for temporarily storing data from the processor;
- a second buffer space for temporarily storing data from the main memory;
- a first analyzer for monitoring data quantity of the first buffer space in a first period of time to determine if the data quantity of the first buffer space exceeds a first threshold value;
- a second analyzer for monitoring data quantity of the second buffer space in a second period of time to determine if the data quantity of the second buffer space exceeds a second threshold value;
- and
- a power management unit, coupled to the first analyzer and the second analyzer, for modifying an operating clock and an operating voltage of the processor, and an operating clock and an operating voltage of the main memory.
9 more elements
Dependencies are inferred from the claim text.