System and methods for adapting to attacks on cryptographic processes on multiprocessor systems with shared cache
AssigneeIntel Corporation
InventorDavid Walter Young
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Abstract
Embodiments of system and method for adapting to attacks of cryptographic processes on multiprocessor systems with shared cache are generally described herein. Other embodiments may be described and claimed.
Claims30
A method for operating a multiprocessor processing system having first and second processing units and a cache that is shared by both the first and second processing units, the method comprising:
- monitoring a number of cache misses on the shared cache that occur during the performance of a first cryptographic process by the first processing unit;
- and
- switching to performing a second cryptographic process by the first processing unit after the number of cache misses exceeds a threshold.
A multiprocessor processing system comprising:
- first and second processing units;
- and
- a cache shared by the first and second processing units,
- the first processing unit to monitor a number of cache misses on the shared cache that occur during the performance of a first cryptographic process by the first processing unit and to switch to performing a second cryptographic process by the first processing unit after the number of cache misses exceeds a threshold.
A system comprising:
- external memory comprising dynamic random access memory (DRAM) to store information used by first and second cryptographic processes;
- and
- a multiprocessor system comprising first and second processing units and a cache shared by the first and second processing units, the first processing unit to monitor a number of cache misses on the shared cache that occur during the performance of the first cryptographic process and to switch to performing the second cryptographic process by the first processing unit after the number of cache misses exceed a threshold.
A computer-readable storage medium that stores instructions for execution by a first processing unit or a multiprocessor system comprising the first processing unit and a second processing units and a cache that is shared by both the first and second processing units, the instructions configuring the first processing unit to perform operations comprising:
- monitoring a number of cache misses on the shared cache that occur during the performance of a first cryptographic process by the first processing unit;
- and
- switching to performing a second cryptographic process by the first processing unit after the number of cache misses exceeds a threshold.
Dependencies are inferred from the claim text.