Mechanism for hardware tracking of return address after tail call elimination of return-type instruction

A method comprising:

• detecting whether a stream of instructions including a first call-type instruction encountered at a first stage of a processor pipeline includes a tail-call elimination instruction sequence of one or more instructions including (i) said first call-type instruction, and (ii) an instruction in a delay slot for said first call-type instruction wherein said instruction in said delay slot is indicative of the tail-call elimination instruction sequence, and further wherein said instruction in the delay slot restores, to a designated location of the processor pipeline, a return address associated with a second call-type instruction after the first call-type instruction saves an associated return address to the designated location;
• and
• maintaining a first return address stack unchanged in response to detection of the tail-call elimination instruction sequence and otherwise pushing a return address associated with the first call-type instruction onto the first return address stack.

An apparatus comprising:

• a speculative execution processor pipeline;
• means for maintaining a stack of return addresses associated with instruction flow at a first stage of the processor pipeline in response to detecting a tail-call elimination sequence of one or more instructions including (i) a first call-type instruction, and (ii) an instruction in a delay slot for said first call-type instruction, wherein said instruction in said delay slot is indicative of the tail-call elimination sequence and further wherein the instruction in the delay slot restores, to a designated location of the processor pipeline, a return address associated with a second call-type instruction after the first call-type instruction saves an associated return address to the designated location of the processor pipeline.