Preventing register data flow hazards in an SST processor

An apparatus for preventing data hazards during simultaneous speculative threading, comprising:

• a processor;
• execution mechanism on the processor;
• wherein the execution mechanism is configured execute instructions in an execute-ahead mode using a first thread, wherein the execution mechanism is configured to maintain dependency information for each register indicating whether the register is subject to an unresolved data dependency;
• upon the resolution of a data dependency during execute-ahead mode, the execution mechanism is configured to copy a dependency information to a speculative copy of the dependency information and to commence execution of the deferred instructions in a deferred mode using a second thread;
• and
• while executing in the deferred mode, if the speculative copy of the dependency information for a destination register indicates that a WAW hazard exists with a subsequent non-deferred instruction executed by the first thread in execute-ahead mode, the execution mechanism is configured to execute the deferred instruction to produce a result and to forward the result to be used by subsequent deferred instructions, without committing the result to the architectural state of the destination register;
• wherein the dependency information includes a “not-there” bit, which indicates whether or not a value to be stored in the register by a preceding instruction is subject to an unresolved data dependency and is consequently not available, and a speculative “not-there” bit, which indicates whether or not the register was subject to an unresolved data dependency when the second thread commenced execution in deferred mode;
• and
• wherein when copying the dependency information to the speculative copy of the dependency information, the execution mechanism is configured to copy the “not-there” bits to the speculative “not-there” bits.

A computer system for preventing data hazards during simultaneous speculative threading, comprising:

• a processor;
• a memory coupled to the processor, wherein the processor stores and retrieves data and instructions from the memory;
• an execution mechanism on the processor;
• wherein the execution mechanism is configured execute instructions in an execute-ahead mode using a first thread, wherein the execution mechanism is configured to maintain dependency information for each register indicating whether the register is subject to an unresolved data dependency;
• upon the resolution of a data dependency during execute-ahead mode, the execution mechanism is configured to copy a dependency information to a speculative copy of the dependency information and to commence execution of the deferred instructions in a deferred mode using a second thread;
• and
• while executing in the deferred mode, if the speculative copy of the dependency information for a destination register indicates that a WAW hazard exists with a subsequent non-deferred instruction executed by the first thread in execute-ahead mode, the execution mechanism is configured to execute the deferred instruction to produce a result and to forward the result to be used by subsequent deferred instructions, without committing the result to the architectural state of the destination register;
• wherein the dependency information includes a “not-there” bit, which indicates whether or not a value to be stored in the register by a preceding instruction is subject to an unresolved data dependency and is consequently not available, and a speculative “not-there” bit, which indicates whether or not the register was subject to an unresolved data dependency when the second thread commenced execution in deferred mode;
• and
• wherein when copying the dependency information to the speculative copy of the dependency information, the execution mechanism is configured to copy the “not-there” bits to the speculative “not-there” bits.