Method and apparatus for performing an atomic semaphore operation
AssigneeQUALCOMM Incorporated
InventorsThomas Philip Speier, James Norris Dieffenderfer, Richard Gerard Hofmann, Thomas Andrew Sartorius
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Abstract
A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus; a memory region coupled to the bus; and a plurality of processing components having access to the memory region over the bus, each of the processing components being configured to perform a semaphore operation to gain access to the memory region by simultaneously requesting a read operation and a write operation to a semaphore location over the bus.
Claims29
A processing system, comprising:
- a bus;
- a memory region coupled to the bus;
- and
- a plurality of processing components having access to the memory region over the bus, each of the processing components being configured to perform a semaphore operation to gain access to the memory region by simultaneously requesting a read and write operation to a same semaphore address over the bus,
- wherein the bus is configured to send multiple instances of the same semaphore address in the same cycle.
A processing system, comprising:
- a bus;
- a memory region coupled to the bus;
- and
- a plurality of processing components having access to the memory region over the bus, each of the processing components having means for performing a semaphore operation to gain access to the memory region by simultaneously requesting a read and write operation to a same semaphore address over the bus,
- wherein the bus is configured to send multiple instances of the same semaphore address in the same cycle.
A method of managing access to a memory region over a bus by a plurality of processing components, the method comprising:
- performing a semaphore operation by one of the processing components to gain access to the memory region, the semaphore operation being performed by simultaneously requesting a read and write operation to a same semaphore address over the bus,
- wherein the bus is configured to send multiple instances of the same semaphore address in the same cycle.
A computer-readable medium comprising instructions, which, when executed by a processing system having a bus, a memory region and a plurality of processing components, cause the processing system to perform operations, the instructions comprising:
- program code to perform a semaphore operation by one of the processing components to gain access to the memory region, the semaphore operation being performed by simultaneously requesting a read and write operation to a same semaphore address over the bus,
- wherein the bus is configured to send multiple instances of the same semaphore address in the same cycle.
Dependencies are inferred from the claim text.