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US 7,610,449 B2Granted
Apparatus and method for saving power in a trace cache
AssigneeInternational Business Machines Corporation
InventorsGordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
Life of this patent
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Abstract
A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.
Claims12
Apparatus comprising:
- a computer system central processor;
- layered memory operatively coupled to said central processor and accessible thereby, said layered memory having a level one cache storing in interchangeable locations both standard cache lines and trace lines;
- and
- a trace cache controller having a directory guiding access to lines stored in said level one cache, the directory having both tag data and size data for stored cache lines, the controller optimizing power requirements in accessing stored cache lines by reading data associated with valid instruction entries;
- said trace cache controller operating level one cache processes at a clock speed which is a fraction of the clock speed of said central processor.
2 more elements
Method comprising:
- coupling together a computer system central processor and layered memory accessible by the central processor;
- selectively storing in interchangeable locations of a level one cache of the layered memory both standard cache lines and trace lines;
- operating trace cache processes at a clock speed which is a fraction of the clock speed of the central processor;
- storing tag data and size data for each stored cache line;
- and
- optimizing power requirements in accessing stored cache lines by reading data associated with valid instruction entries.
3 more elements
Programmed method comprising:
- coupling together a computer system central processor and layered memory accessible by the central processor, the layered memory including a level one cache;
- selectively storing in interchangeable locations of the level one cache of the layered memory both standard cache lines and trace lines;
- operating trace cache processes at a clock speed which is a fraction of the clock speed of the central processor;
- storing tag data and size data for each stored cache line;
- and
- optimizing power requirements in accessing stored cache lines by reading data associated with valid instruction entries.
3 more elements
Dependencies are inferred from the claim text.