Method and system for hardware implementation of resetting an external two-wired EEPROM

Abstract

Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Dependencies are inferred from the claim text.