Integrated circuit tester information processing system

A method for operating an integrated circuit tester information processing system comprising:

• measuring current information from test structures for an integrated circuit having dual stress liners with the test structures including parallel test structures and orthogonal test structures;
• selecting a drain current high (Idhigh) and a drain current low (Idlow) for each of the test structures from the current information or stored current information;
• deriving a parallel proximity scaling factor (kx1) and an orthogonal proximity scaling factor (ky) for a stress contribution based on an active area of a circuit element in the integrated circuit with the drain current high (Idhigh) and the drain current low (Idlow) for each of the test structures including:
• calculating an effective drain current (Ideff) for each of the test structures with the drain current high (Idhigh) and the drain current low (Idlow),
• providing an equation for a stress component with a distance between the active area and a stress liner of the dual stress liners,
• relating a change in the effective drain current to a change of mobility in the circuit element, and
• relating the equation and the change to mobility for deriving the scaling factor;
• and
• correlating the stress contribution with the integrated circuit.

An integrated circuit tester information processing system comprising:

• measurement circuitry for measuring current information from test structures for an integrated circuit having dual stress liners;
• extraction circuitry for selecting currents from the current information or stored current information;
• analysis circuitry for deriving a scaling factor with the currents for a stress contribution based on an active area of a circuit element in the integrated circuit;
• and
• presentation circuitry for correlating the stress contribution with the integrated circuit.