Counter of semiconductor device

A 2-bit counter, comprising:

• a first unit counter block, comprising a D-flipflop, a second selector to select one from external data and a second output signal of the D-flipflop in response to a data load signal and output a selected signal, and a first selector to transfer one from a first output signal of the D-flipflop and the output signal of the second selector as an input signal of the D-flipflop in response to a counter enable signal or the data load signal;
• and
• a second unit counter block, comprising a D-flipflop, a second selector to select one from external data and a second output signal of the D-flipflop in response to a data load signal and output a selected signal, and a first selector to transfer one from a first output signal of the D-flipflop and the output signal of the second selector as an input signal of the D-flipflop in response to the output signal of the second selector of the first counter block and a counter enable signal or the data load signal.

An n-bit counter, comprising

• n counter blocks respectively comprising a D-flipflop, a second selectors to select one from external data and a second output signal of the D-flipflop in response to a data load signal and output a selected signal, and a first selector to transfer one from a first output signal of the D-flipflop and the output signal of the second selector as an input signal of the D-flipflop in response to a counter enable signal or the data load signal,
• wherein an mth counter block outputs an mth bit signal that is toggled in a period where all output signals of the second selectors included in first to (m−1)th counter blocks are at a first level and the counter enable signal is at a second level.