Circuit, system, and method for multiplexing signals with reduced jitter

A system, comprising:

• a circuit comprising three logic gates and a logic block, each arranged within a separate power domain, wherein:
• a first of the three logic gates is coupled for receiving a first signal;
• a second of the three logic gates is coupled for receiving a second signal;
• and
• a third of the three logic gates is coupled for receiving only one of the first and second signals, depending on a state of a control signal supplied to the first and second logic gates from the logic block;
• and
• at least one system component coupled to an output of the third logic gate for receiving the only one of the first and second signals.

A method for multiplexing signals with reduced jitter, the method comprising:

• supplying a first signal to a first logic gate and a second signal to a second logic gate;
• deactivating one of the first or second signals by supplying a control signal to the first and second logic gates;
• and
• forwarding an active one of the first or second signals to a third logic gate, wherein the steps of deactivating and forwarding enable the first and second signals to be multiplexed with reduced jitter, and wherein the first, second and third logic gates are spaced apart from one another and respectively arranged within a first, second and third power domain.