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US 7,609,758 B2Granted
Method of phase shifting bits in a digital signal pattern
AssigneeAgilent Technologies, Inc.
InventorRoger L. Jungerman
Life of this patent
Estimating the term…
Abstract
A method of phase shifting bits in a digital signal pattern combines a bit-wise phase-shift signal with an external clock signal to produce a perturbed clock signal. The perturbed clock signal is provided to a digital pattern source to generate a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal.
Claims15
A method of phase shifting bits in a digital signal pattern comprising:
- applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
- providing the perturbed clock signal to a digital pattern source;
- and
- generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
- wherein the bit-wise phase-shift signal comprises a sum of a plurality of digital signals from a plurality of digital pattern generators, the plurality of digital signals are combined in a binary ladder.
2 more elements
A method of phase shifting bits in a digital signal pattern comprising:
- applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
- providing the perturbed clock signal to a digital pattern source;
- and
- generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
- wherein the bit-wise phase-shift signal comprises a sum of a plurality of digital signals from a plurality of digital pattern generators;
- wherein the plurality of digital signals are combined in a binary ladder;
- and
- wherein the plurality of digital pattern generators comprises bit error ratio tester modules.
5 more elements
A method of phase shifting bits in a digital signal pattern comprising:
- applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
- providing the perturbed clock signal to a digital pattern source;
- and
- generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
- wherein the step of applying the bit-wise phase-shift signal to the clock signal comprises adding the bit-wise phase-shift signal to the clock signal in a resistive combiner.
2 more elements
A method of phase shifting bits in a digital signal pattern comprising:
- applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
- providing the perturbed clock signal to a digital pattern source;
- and
- generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
- wherein the step of applying the bit-wise phase-shift signal to the clock signal comprises providing the clock signal to a quadrature hybrid coupler, attenuating at least a first output of the quadrature hybrid coupler according to the bit-wise phase-shift signal, and adding the first output of the quadrature hybrid coupler to a second output of the quadrature hybrid coupler.
2 more elements
A method of phase shifting bits in a digital signal pattern comprising:
- applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
- providing the perturbed clock signal to a digital pattern source;
- and
- generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
- and further comprising steps, prior to the step of applying the bit-wise phase-shift signal, of:
- measuring data-dependent jitter of the digital signal pattern;
- determining a worst-case data dependent jitter transition;
- and
- selecting a digital level sufficient to correct the worst-case data-dependent jitter transition.
6 more elements
A method of phase shifting bits in a digital signal pattern comprising:
- applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
- providing the perturbed clock signal to a digital pattern source;
- and
- generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
- further comprising steps, prior to the step of combining the bit-wise phase-shift signal, of:
- measuring data-dependent jitter of the digital signal pattern;
- determining a worst-case data dependent jitter transition;
- and
- selecting a digital level sufficient to correct the worst-case data-dependent jitter transition;
- further comprising the step of:
- programming a jitter reference source to generate the digital level in the bit-wise phase-shift signal and further comprising steps, after the step of calculating a digital level, of:
- calculating digital signal levels sufficient to compensate a plurality of data-dependent jitter transitions in the digital signal pattern;
- generating the bit-wise phase-shift signal to compensate the plurality of data-dependent jitter transitions in the shifted digital signal pattern,
- wherein a digital pattern generator of the plurality of synchronized digital pattern generators provides a voltage level different from each of a remainder of the plurality of digital pattern generators;
- and
- wherein a first digital pattern generator produces a first voltage level and a second digital pattern generator produces a second voltage level, the first voltage level being 2n times the second voltage level, where n is an integer.
13 more elements
Dependencies are inferred from the claim text.