High speed multiplexer with parallel architecture

An electronic multiplexing circuit for time-division multiplexing two initial NRZ-type, binary-coded signals, each bit of the signals having a duration T, the two signals being able to take respective values defining four states denoted “0, 0”, “0, 1”, “1, 0”, “1, 1”, said circuit comprising:

• a generator of four primary signals respectively associated with said four states:
• a first continuous primary signal of amplitude corresponding to the “0” binary level;
• a second continuous primary signal of amplitude corresponding to the “1” binary level;
• a third periodic primary signal comprising a succession of bits alternating between the “0” and “1” binary levels, each bit of said third signal having a duration T/2, half the duration of the bits of the initial signals;
• A fourth periodic primary signal comprising a succession of bits alternating between the “0” and “1” binary levels, each bit of said fourth signal having a duration T/2, half the duration of the bits of the initial signals, said fourth signal being phase-shifted by a duration of one bit relative to the third signal;
• and
• electronic selection means for selecting said primary signals controlled by the two initial NRZ signals for generating a final multiplexed signal from the four primary signals, said means being arranged so that, for each duration T for which the two initial NRZ signals define a given state, the final multiplexed signal results from the selection during the duration T of the one of the four primary signals that is associated with said given state.