Selective edge phase mixing

A selective edge phase mixing unit, comprising:

• a first logic gate to receive a clock signal, and to receive first control signals;
• pull-up circuits coupled to an output of the first logic gate and to receive the first control signals;
• a second logic gate to receive the clock signal, and to receive second control signals;
• and
• pull-down circuits coupled to an output of the second logic gate and to receive the second control signals, wherein the pull-up circuits and the pull-down circuits communicate with an output that provides a duty cycle corrected clock signal.

A selective edge phase mixing unit, comprising:

• a first logic gate coupled to a clock signal through an input port and coupled to first control signals;
• a first pull-up interpolation circuit coupled between a power supply voltage and an output operable to receive an output of the first logic gate and to the first control signals;
• a second pull-up interpolation circuit coupled between the power supply voltage and the output operable to receive the first control signals and an output of the first pull-up interpolation circuit through a first interstage logic;
• a second logic gate coupled to the clock signal and coupled to second control signals;
• a first pull-down interpolation circuit coupled between a potential and the output that is operable to receive an output of the second logic gate and the second control signals;
• and
• a second pull-down interpolation circuit coupled between the potential and the output that is operable to receive the second control signals and an output of the first pull-down interpolation circuit through a second interstage logic circuit;
• wherein the output port provides a duty cycle corrected clock signal.

An electronic system, comprising:

• a processor;
• a memory device including an array of memory cells that is operatively coupled to the processor, wherein the processor is configured to perform operations on the array of memory cells in synchronization with transitions of an externally provided clock signal;
• and
• a selective edge phase mixing unit, the mixing unit comprising:
• a first logic gate in communication with the externally provided clock signal and responsive to first control signals;
• pull-up circuits in communication with an output of the first logic gate and responsive to the first control signals;
• a second logic gate in communication with the externally provided clock signal and responsive to second control signals;
• and
• pull-down circuits coupled to an output of the second logic gate and with the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to an output that provides a duty cycle corrected clock signal to the memory device.

A method, comprising:

• receiving a non-adjusted clock signal at an input;
• receiving at least one duty cycle adjustment signal generated by an edge phase mixing unit that includes a first logic gate and a second logic gate coupled to the input, the first logic gate being coupled a pull-up interpolation circuit that is further coupled to an output, wherein the pull-up interpolation circuit receives one of the duty cycle adjustment signals, the second logic gate being coupled to a pull-down interpolation circuit that is further coupled to the output, wherein the pull-down interpolation circuit is configured to receive another one of the duty cycle adjustment signals;
• and
• adjusting a duty cycle of the non-adjusted clock signal in response to the received duty cycle adjustment signal.