US 7,609,578 B2 · Quad SRAM based one time programmable memory

Abstract

A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell.

Claims19

Dependent claims

A one-time programmable memory cell, comprising:

a storage element having a first upper input, a second upper input opposite the first upper input, a first lower input, a second lower input opposite the first lower input, a first output, and a second output opposite the first output;
a first fuse coupled to the first upper input, wherein the first fuse, when programmed, acts as a pull-up device on the first output;
a second fuse coupled to the second upper input, wherein the second fuse, when programmed, acts as a pull-up device on the second output;
a third fuse coupled to the first lower input, wherein the third fuse, when programmed, acts a pull-down device on the first output;
and
a fourth fuse coupled to the second lower input, wherein the fourth fuse, when programmed, acts a pull-down device on the second output.

3 more elements

A non-volatile dual SRAM one-time programmable memory device, comprising:

a dual SRAM one-time programmable memory block including one or more dual SRAM one-time programmable memory cells, wherein a dual SRAM one-time programmable memory cell operates as an SRAM memory cell prior to programming and operates as a one-time programmable memory cell after programming;
an SRAM module coupled to the dual SRAM one-time programmable memory block, wherein the SRAM read/write module is configured to read from and write to one or more dual SRAM one-time programmable memory cells prior to programming;
and
an one-time programmable module configured to program one or more one-time programmable memory cells and to read one or more one-time programmable memory cells after programming.

1 more element

Dependencies are inferred from the claim text.

Quad SRAM based one time programmable memory

Life of this patent

Quad SRAM based one time programmable memory

Life of this patent

Abstract

Claims19